5. The block diagram of Figure 5 shows a 3-stage asynchronous counter
that is used to count a series of randomly occuring input pulses.
The q outputs of the counter are used to drive a logic circuit that gives the output in TABLE 1.
(a) Counter DesignImages Not ShownConsider Table 1 in the XXXXX XXXXX. XX XXXXX the expected XXXXXX XX the counter for XXX XXXXX pulses (i.e as XXXXX XXXXX goes XXXX 0 XX X the bits Q3 XX Q1 should show XXX XXXXXXXXXXXXX binary XXXXXXXXXXXXXX). From XXX table we XXX XXX,
XXXXXX that XX, XXX XXXXX XXXXXXXXXXX XXX (XXX), toggles for every XXXXX pulse. So we XXXXX use XXX XXXXX as clock to XXX XXXXX flip XXXX XXXX XXXXXXX the XXXXXXXXXX, XX find XXXX for every transition XX Q1 from X to 0, Q2 toggles XXX XXXXX. XX XX use Q1 XX clock the XXXXXX XXXX flop. XXXXXXXX since 1->X XXXXXXXXXX XX the trigger, we use XXXXXXXX XXXX triggered XXXX flops.XXXXXXX to XXXXX (2) we XXX see that Q3 XXXXXXX XXX XXXXX 1-&XX;0 XXXXXXXXXX XX Q2. Hence XX is XXXX XX clock XXX third XXX XXXXX XXXX XXXX
X D XXXX flop XXXXXXXX the input XXXXX to XXXXXX when XXXXXXXXX. From XXX points above XX XXXX XXXX we want XXXX output XXX XX toggle when XXXXXXXXX. XX we XXXXXXX Images Not Shown XX XXXX flip XXXX XXXX to XXX input Images Not Shown.
XXX preset and XXXXX XXXX of the flip flops XXX XXXXXX XXX XXX hence connected to Images Not Shown
Fig1 in XXX XXXXX XXXXX XXXXX the complete XXXXXXX circuit. Fig 2 in the same XXXXX displays the XXXXXX XXXXXXX XXXXX on XXX counter XXXXXXX explained above.
(b) XXXXX circuit XXXXXX.
XX XXXX the XXXXX table XXX XXXXX pulse v/s counter XXXXXX XXXX XXXXX in part (a).
Part (b) XX the XXXXXXXX XXXXX us XXX table XXX XXXXX pulse v/s logic circuit XXXXXX.
So XX XXX get the truth table for (XX Q2 XX) and (X C B X) shown in the XXXXX below.
Using this table XX XXX solve XXX K-maps for each XXXXXX and express XXXX in XXXXX of Q3, XX, XX
XX can be XXXX XXXX the image:
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as noticed XXXX tableImages Not Shown
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Corresponding XXXXX circuit XXX be XXXXX in the XXXXXXXXX XXXXX.
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