Name
Professor
Course
Date
Question: 1
01: Analyze the data dependence in the given instruction sequence. (6')
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Dependence? (Which $ is depend on which $? Type?)
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add $t0, $t1, $t2
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NA
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sub $t3, $t0, $t3
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Register $t3 is dependent on St0. RAW dependence with first dependence
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lw $t5, 0($t0)
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Register $t5 is dependent on St0 of the first instruction. RAW dependency with first instruction
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beq $t5, $t6, BRANCH
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RAW dependency with third instruction
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Q2: In an ideal 5-stage pipelining, with total number of instruction being n, number of cycles needed to execute entire instructions = 5 + (n-) = n + 4 cycles
Since n=4, hence total number of cycles taken = 4 + 4 = 8 cycles
Q3: Below is the pipelining diagram:-
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1
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2
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3
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4
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5
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6
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7
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8
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9
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10
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11
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12
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add $t0, $t1, $t2
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IF
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ID
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EX
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MEM
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WB
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Nop
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XX
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XX
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XX
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MEM
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WB
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Nop
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IF
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XX
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EX
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XXX
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WB
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sub $t3, $XX, $t3
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XX
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XX
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EX
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MEM
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XX
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lw $t5, 0($XX)
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IF
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XX
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EX
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MEM
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WB
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XXX
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IF
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ID
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XX
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XXX
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XX
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Nop
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XX
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ID
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EX
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XXX
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XX
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XXX $XX, $XX, BRANCH
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IF
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XX
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EX
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MEM
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XX
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As clear from the pipeline-XXXXXX diagram, XXXXXXXXX with Nop will XXXX XX cycles because XXXXXXX forwarding, a XXXXXXXXX instruction has to wait at EX stage for XXX independent instruction XX XXXXXXXX its WB XXXXX.
Q4. Now when XXXX forwarding XX implemented, then XXXXX XX XXX XXXXXX XXXXXXX:-
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1
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X
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X
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X
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X
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X
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X
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X
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X
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add $t0, $t1, $XX
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XX
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ID
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EX
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MEM
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WB
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sub $XX, $XX, $t3
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XX
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XX
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EX
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MEM
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WB
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XX $XX, X($t0)
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IF
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XX
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XX
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MEM
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XX
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XXX
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XX
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ID
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XX
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MEM
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XX
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beq $XX, $XX, XXXXXX
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IF
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XX
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XX
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MEM
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WB
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XXXX in full XXXXXXXXXX, in case of XXX dependency, the result produced XX pervious dependent XXXXXXXXXXX XX immediately XXXXXXXXX to XXXX XXXXXXXXX XXXXXXXXXXX XX EX stage XX XXXX XXXXXXXXX
Instruction. Hence, there XX XX delay if the previous XXXXXXXXXXX XX R-XXXX or XXXXXXXXX XXXX instruction.
However if pervious XXXXXXXXXXX is XXXX/XXXXX XXXX XX XXXXXXXXXXX then XXX XXXX instruction XXX XX XXXX XXX the pervious instruction XX XXXXXX at XXX stage and XXXX forward XXX XXXXXX. Hence, there is 1 cycle delay in XXX XXXX XXXXXXXXXXX when XXX previous instruction is load/XXXXX XXXX XX XXXXXXXXXXX, which XX XXX I have XXXXX a Nop instruction XXXXXXX third XXX XXXXXX XXXXXXXXXXX.
Question X
Q.1XXX XX XXXXXXXXXXX XX used XX store a register XXXXX into Memory. XXXX XXXXX the values of the signals given:
Signal
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Value (in decimal)
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XXXXXXXX XXXXX
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XXXX Addr 1
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8
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XXXX XXXX X
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7
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Read XXXX 1
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XXX
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XXXX Data X
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70
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XXXX Memory
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XXXXX Data
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100
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XXXXX Address
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XXX
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RegWrite
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X
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MemWrite
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X
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XXXXXXX
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0
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ALUScr
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1
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The read addr 1 XX XXX rs register i.e. R8, XXXX data X is XXX XXXXX of XXXX register, XXXXX XX added to XXX offset to XXX XXX XXXXX address, XXX Write XXXX is same as XXXX dtat2. The XXXXXXX signals XXXXXXX that Memory XXXX to be XXXXXXX XXX XXXX XXX XXXXXX with XXX XXXX XXXX 1 value.
X.X: XXXX, XXX Load Word XXXXXXXXXXX XXXX XXX XXXXX XX the XXXXXX location 200 into regiter R7.XX.R7->XX
Then ADD XXXXXXXXXXX XXXX XX XXX XX and stores the result XXXX R7.XX->XX
XXXXXXX, the XX instructions stores XXX value XX XX into XXX Address 204. i.e XXX (XXX) = 70
Hence, the final XXXXXX register file and XXXXXX XXXXXXXX execution are as XXXXX:
Register
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Value
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XX
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XX
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R7
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70
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R8
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200
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Memory Location
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Values
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XXX
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20
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204
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70
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XXX
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156
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XXXXXXXX: X
Assuming XXXX we are using the XXXXXX implementation XX Multiplication circuits. What are the XXXXXXX in XXX registers when we XXXXXXXXX 110o x XXXX? XXXX the table.
XXXXXXXXX
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XXXX
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Multiplier
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XXXXXXXXXXXX
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XXXXXXX
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X
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XXXXXXX
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1010
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1100
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XXXX 000
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1
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XXXXX right of XXXXXXXXXXXX(Q)
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XXXX
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1100
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XXXX XXXX
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X
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XXX X + X
Shift right X
XXXXX right X
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1100
0110
0010
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XXXX
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0110 0010
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X
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XXXXX right Q
Shift right X
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0001
XXXX
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XXXX
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XXXX 0010
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4
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XXX A + B
Shift XXXXX X
XXXXX XXXXX X
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XXXX
0110
XXXX
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XXXX
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0111 1000
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XXXXXXXXX, the final product XX;
XXXXXXXX = 120 (1010 =XX
XXXX = XX
XX x 12 = XXX)
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